Image sensor arrays typically comprise a linear array of photosensors which raster scan an image bearing document and convert the microscopic image areas viewed by each photosensor to image signal charges. Following an integration period, the image signal charges are amplified and transferred as an analog video signal to a common output line or bus through successively actuated multiplexing transistors.
For high-performance image sensor arrays, a preferred design includes an array of photosensors of a width comparable to the width of a page being scanned, to permit one-to-one imaging generally without the use of reductive optics. In order to provide such a "full-width" array, however, relatively large silicon structures must be used to define the large number of photosensors. A preferred technique to create such a large array is to align several butted silicon chips, each chip defining a small linear array thereon. In one proposed design, an array is intended to comprise up to twenty silicon chips, butted end-to-end, each chip having 248 active photosensors spaced at 400 photosensors per inch.
The silicon chips which are butted to form a single full-width array are typically created by first creating the circuitry for a plurality of individual chips on a single silicon wafer. The silicon wafer is then cut, or "diced," around the circuit areas to yield discrete chips. Typically, the technique for dicing the chips includes a combination of chemical etching and mechanical sawing. Because, on each chip, the photosensors are spaced with high resolution from one end of a chip to the other, the length of each diced chip from one end of the array thereon to the other requires precision dicing. It would be desirable to dice each individual chip with a precise dimension along the linear array of photosensors, so that, when a series of chips are butted end-to-end to form a single page-width linear array, there is a minimum disruption of spacing from an end photosensor on one chip to a neighboring photosensor at the end of a neighboring chip. Ideally, the spacing, or pitch, across an entire full-width linear array should be consistent regardless of the configuration of silicon chips forming the array.